1017 search results - page 52 / 204 » A routing algorithm for flip-chip design |
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
DAC
1997
ACM
14 years 1 months ago
1997
ACM
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
ISLPED
2010
ACM
13 years 9 months ago
2010
ACM
This paper proposes a framework for (signal) interconnect power optimization at the global routing stage. In a typical design flow, the primary objective of global routing is mini...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
Conventional global routing minimizes total wire length and congestion. Experiments using large industrial benchmark circuits show that up to 24% of nets in such routing solutions...
ICPADS
2005
IEEE
14 years 2 months ago
2005
IEEE
— The Distributed Spanning Tree (DST) is an overlay structure designed to be scalable. It supports the growth from small scale to large scale. The DST is a tree without bottlenec...