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» A routing algorithm for flip-chip design
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ICCD
2008
IEEE
120views Hardware» more  ICCD 2008»
14 years 5 months ago
Near-optimal oblivious routing on three-dimensional mesh networks
— The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip architecture innovations. One direction is in the extens...
Rohit Sunkam Ramanujam, Bill Lin
NOSSDAV
2009
Springer
14 years 3 months ago
A delaunay triangulation architecture supporting churn and user mobility in MMVEs
This article proposes a new distributed architecture for update message exchange in massively multi-user virtual environments (MMVE). MMVE applications require delivery of updates...
Mohsen Ghaffari, Behnoosh Hariri, Shervin Shirmoha...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
14 years 27 days ago
Safe Delay Optimization for Physical Synthesis
-- Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the final result, often by neg...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
ORL
2010
85views more  ORL 2010»
13 years 7 months ago
Stable routing under the Spanning Tree Protocol
The Spanning Tree Protocol routes traffic on shortest path trees. If some edges fail, the traffic has to be rerouted consequently, setting up alternative trees. In this paper we d...
Fabrizio Grandoni, Gaia Nicosia, Gianpaolo Oriolo,...
EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
14 years 1 months ago
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng