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PACS
2004
Springer
115views Hardware» more  PACS 2004»
14 years 22 days ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
JUCS
2006
112views more  JUCS 2006»
13 years 7 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
CCGRID
2009
IEEE
14 years 2 months ago
BLAST Application with Data-Aware Desktop Grid Middleware
—There exists numerous Grid middleware to develop and execute programs on the computational Grid, but they still require intensive work from their users. BitDew is made to facili...
Haiwu He, Gilles Fedak, Bing Tang, Franck Cappello
MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
14 years 2 months ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
SECON
2008
IEEE
14 years 1 months ago
Coordinated Locomotion of Mobile Sensor Networks
Stationary wireless sensor networks (WSNs) fail to scale when the area to be monitored is open (i.e borderless) and the physical phenomena to be monitored may migrate through a la...
Seokhoon Yoon, Onur Soysal, Murat Demirbas, Chunmi...