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ASPDAC
2011
ACM
297views Hardware» more  ASPDAC 2011»
12 years 11 months ago
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...
Shashikanth Bobba, Ashutosh Chakraborty, Olivier T...
ICCD
2006
IEEE
77views Hardware» more  ICCD 2006»
14 years 4 months ago
Iterative-Constructive Standard Cell Placer for High Speed and Low Power
Abstract— Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still...
Sungjae Kim, Eugene Shragowitz
SLIP
2009
ACM
14 years 2 months ago
A pre-placement net length estimation technique for mixed-size circuits
An accurate model for pre-placement wire length estimation can be a useful tool during the physical design of integrated circuits. In this paper, an a priori wire length estimatio...
Bahareh Fathi, Laleh Behjat, Logan M. Rakai
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 1 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
ISQED
2007
IEEE
104views Hardware» more  ISQED 2007»
14 years 1 months ago
System Level Estimation of Interconnect Length in the Presence of IP Blocks
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh