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GLVLSI
2003
IEEE
177views VLSI» more  GLVLSI 2003»
14 years 29 days ago
Congestion reduction in traditional and new routing architectures
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
Ameya R. Agnihotri, Patrick H. Madden
FCCM
1998
IEEE
113views VLSI» more  FCCM 1998»
13 years 12 months ago
PAM-Blox: High Performance FPGA Design for Adaptive Computing
PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High- performance FPGA design for adaptive computing is simplified by using a ...
Oskar Mencer, Martin Morf, Michael J. Flynn
ISPD
1997
ACM
100views Hardware» more  ISPD 1997»
13 years 12 months ago
A pseudo-hierarchical methodology for high performance microprocessor design
- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for...
A. Bertolet, K. Carpenter, Keith M. Carrig, Albert...
FPGA
1995
ACM
149views FPGA» more  FPGA 1995»
13 years 11 months ago
PathFinder: A Negotiation-based Performance-driven Router for FPGAs
Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused...
Larry McMurchie, Carl Ebeling
ICCAD
2010
IEEE
146views Hardware» more  ICCAD 2010»
13 years 5 months ago
Through-silicon-via management during 3D physical design: When to add and how many?
In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger a...
Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Ky...