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» A statistical multiprocessor cache model
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ICML
2008
IEEE
14 years 10 months ago
Memory bounded inference in topic models
What type of algorithms and statistical techniques support learning from very large datasets over long stretches of time? We address this question through a memory bounded version...
Ryan Gomes, Max Welling, Pietro Perona
GLVLSI
2010
IEEE
190views VLSI» more  GLVLSI 2010»
13 years 11 months ago
A linear statistical analysis for full-chip leakage power with spatial correlation
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong
ACL
2007
13 years 11 months ago
Extending MARIE: an N-gram-based SMT decoder
In this paper we present several extensions of MARIE1 , a freely available N-gram-based statistical machine translation (SMT) decoder. The extensions mainly consist of the ability...
Josep Maria Crego, José B. Mariño
SC
1991
ACM
14 years 1 months ago
Delayed consistency and its effects on the miss rate of parallel programs
In cache based multiprocessors a protocol must maintain coherence among replicated copies of shared writable data. In delayed consistency protocols the effect of out-going and in-...
Michel Dubois, Jin-Chin Wang, Luiz André Ba...
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
13 years 11 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...