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» A statistical multiprocessor cache model
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ICPP
2009
IEEE
13 years 5 months ago
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
14 years 1 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
DAC
2004
ACM
14 years 8 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
DATE
2007
IEEE
71views Hardware» more  DATE 2007»
14 years 1 months ago
Task scheduling for reliable cache architectures of multiprocessor systems
This paper presents a task scheduling method for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the ...
Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
EUROPAR
2008
Springer
13 years 9 months ago
Exploration of the Influence of Program Inputs on CMP Co-scheduling
Recent studies have showed the effectiveness of job co-scheduling in alleviating shared-cache contention on Chip Multiprocessors. Although program inputs affect cache usage and thu...
Yunlian Jiang, Xipeng Shen