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» A strategy for MINLP synthesis of flexible and operable proc...
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ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
13 years 9 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
TC
2011
13 years 2 months ago
An Architecture for Fault-Tolerant Computation with Stochastic Logic
—Mounting concerns over variability, defects and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signa...
Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan...
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Node Mergers in the Presence of Don't Cares
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...
EDOC
2006
IEEE
14 years 1 months ago
Net-Centric Information Management
Information sharing is a key tenet of network-centric warfare (NCW). Information sharing succeeds when the right information is provided to the right people at the right time and ...
Scott Renner
CAMP
2005
IEEE
14 years 1 months ago
An Intelligent and Task-Independent Controller for Video Sequence Analysis
—This paper describes a task-independent controller that allows for an easy implementation of vision systems for processing video sequences. The controller does not have a fixed ...
José Bins, Thor List, Robert B. Fisher, Dav...