65 search results - page 10 / 13 » A strategy for testing hardware write block devices |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
DFT
2007
IEEE
14 years 2 months ago
2007
IEEE
The network-on-chip (NoC) paradigm is seen as a way of facilitating the integration of a large number of computational and storage blocks on a chip to meet several performance and...
DAC
2007
ACM
13 years 11 months ago
2007
ACM
While cryptographic algorithms are usually strong against mathematical attacks, their practical implementation, both in software and in hardware, opens the door to side-channel at...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
The reality of multi-core hardware has made concurrent programs pervasive. Unfortunately, writing correct concurrent programs is difficult. Addressing this challenge requires adva...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
Design variability due to die-to-die and within-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-p...