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» A structural approach to latency prediction
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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 3 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
MICRO
2002
IEEE
164views Hardware» more  MICRO 2002»
14 years 3 months ago
A quantitative framework for automated pre-execution thread selection
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...
Amir Roth, Gurindar S. Sohi
CASES
2006
ACM
14 years 1 months ago
Improving the performance and power efficiency of shared helpers in CMPs
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi...
MIDDLEWARE
2010
Springer
13 years 8 months ago
FaReCast: Fast, Reliable Application Layer Multicast for Flash Dissemination
Abstract. To disseminate messages from a single source to a large number of targeted receivers, a natural approach is the tree-based application layer multicast (ALM). However, in ...
Kyungbaek Kim, Sharad Mehrotra, Nalini Venkatasubr...
MIDDLEWARE
2009
Springer
14 years 2 months ago
Automatic Stress Testing of Multi-tier Systems by Dynamic Bottleneck Switch Generation
Abstract. The performance of multi-tier systems is known to be significantly degraded by workloads that place bursty service demands on system resources. Burstiness can cause queu...
Giuliano Casale, Amir Kalbasi, Diwakar Krishnamurt...