88 search results - page 4 / 18 » A succinct memory model for automated design debugging |
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
Light-weight, flexible access control, which allows software to regulate reads and writes to any granularity of memory region, can help improve the reliability of today’s multi...
CHI
2006
ACM
14 years 7 months ago
2006
ACM
In this paper, we describe our approach to designing interface components that automate the logging of user input. These recorded logs of user-system interactions can serve as a b...
ICCAD
2000
IEEE
13 years 11 months ago
2000
IEEE
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
EUROPAR
2010
Springer
13 years 7 months ago
2010
Springer
Abstract. This paper is motivated by the desire to provide an efficient and scalable software cache implementation of OpenMP on multicore and manycore architectures in general, and...
DAC
2005
ACM
14 years 7 months ago
2005
ACM
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...