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CCECE
2006
IEEE
14 years 1 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
14 years 1 months ago
Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint
The energy-aware design for electronic systems has been an important issue in hardware and/or software implementations, especially for embedded systems. This paper targets a synth...
Heng-Ruey Hsu, Jian-Jia Chen, Tei-Wei Kuo
FCCM
2004
IEEE
133views VLSI» more  FCCM 2004»
13 years 11 months ago
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
Intrusion detection for network security is a computation intensive application demanding high system performance. System level design, a relatively unexplored field in this area,...
Zachary K. Baker, Viktor K. Prasanna
WCE
2007
13 years 8 months ago
Optimizing Designs based on Risk Approach
— In this paper a new approach to optimize nuclear power plant designs based on global risk reduction are described. In design the focus is on as components quality as redundancy...
Jorge E. Núñez Mc Leod, Selva S. Riv...
ICCAD
2005
IEEE
100views Hardware» more  ICCAD 2005»
14 years 4 months ago
Performance-centering optimization for system-level analog design exploration
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih C...