118 search results - page 21 / 24 » A technique for minimizing power during FPGA placement |
HIPC
2007
Springer
14 years 1 months ago
2007
Springer
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
IAJIT
2007
13 years 7 months ago
2007
: Mobile ad-hoc network is a network without infrastructure where every node has its own protocols and services for powerful cooperation in the network. Every node also has the abi...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...