118 search results - page 7 / 24 » A technique for minimizing power during FPGA placement |
FCCM
1999
IEEE
13 years 11 months ago
1999
IEEE
The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that...
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Increasing power densities in Field Programmable Gate Arrays (FPGAs) have made them susceptible to thermal problems. The advent of platform FPGAs has further exacerbated the probl...
SAC
2010
ACM
13 years 7 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...