563 search results - page 38 / 113 » A theory-based alternative for the design of instruction: fu... |
INFOCOM
2000
IEEE
14 years 1 months ago
2000
IEEE
We present a framework for designing end-to-end congestion control schemes in a network where each user may have a different utility function and may experience non-congestion-re...
ERSA
2007
13 years 10 months ago
2007
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
ISCA
2007
IEEE
14 years 3 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
SIGOPS
2011
13 years 4 months ago
2011
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...