563 search results - page 53 / 113 » A theory-based alternative for the design of instruction: fu... |
SAC
2006
ACM
14 years 3 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
ICICIC
2006
IEEE
14 years 3 months ago
2006
IEEE
Traditional nonlinear filtering techniques are observed in underutilization of blur identification techniques, and vice versa. To improve blind image restoration, a designed edg...
MICRO
2005
IEEE
14 years 2 months ago
2005
IEEE
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
ICPP
2000
IEEE
14 years 1 months ago
2000
IEEE
This work considers the use of a n S M T (simultaneous multithreading) processor in lieu of the conventional processor(s) in a router and evaluates quantitatively the potential ga...
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...