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HPCA
2000
IEEE
14 years 1 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
DAC
2002
ACM
14 years 10 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
EMSOFT
2005
Springer
14 years 2 months ago
Model-based analysis of distributed real-time embedded system composition
Key challenges in distributed real-time embedded (DRE) system developments include safe composition of system components and mapping the functional specifications onto the target...
Gabor Madl, Sherif Abdelwahed
DSN
2008
IEEE
13 years 10 months ago
Experiences with formal specification of fault-tolerant file systems
Fault-tolerant, replicated file systems are a crucial component of today's data centers. Despite their huge complexity, these systems are typically specified only in brief pr...
Roxana Geambasu, Andrew Birrell, John MacCormick
FPGA
2008
ACM
133views FPGA» more  FPGA 2008»
13 years 10 months ago
Vector processing as a soft-core CPU accelerator
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
Jason Yu, Guy Lemieux, Christopher Eagleston