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DAC
2010
ACM
13 years 10 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
HPCA
2008
IEEE
14 years 10 months ago
Address-branch correlation: A novel locality for long-latency hard-to-predict branches
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zho...
ASPLOS
2010
ACM
14 years 4 months ago
Request behavior variations
A large number of user requests execute (often concurrently) within a server system. A single request may exhibit fluctuating hardware characteristics (such as instruction comple...
Kai Shen
CORR
2006
Springer
109views Education» more  CORR 2006»
13 years 9 months ago
On Conditional Branches in Optimal Decision Trees
The decision tree is one of the most fundamental ing abstractions. A commonly used type of decision tree is the alphabetic binary tree, which uses (without loss of generality) &quo...
Michael B. Baer
DAC
2009
ACM
14 years 10 months ago
Dynamic thermal management via architectural adaptation
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
Ramkumar Jayaseelan, Tulika Mitra