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ICCAD
2010
IEEE
158views Hardware» more  ICCAD 2010»
13 years 5 months ago
Novel binary linear programming for high performance clock mesh synthesis
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Minsik Cho, David Z. Pan, Ruchir Puri
FSTTCS
2007
Springer
13 years 11 months ago
Efficient and Expressive Tree Filters
Abstract. We investigate streaming evaluation of filters on XML documents, evaluated both at the root node and at an arbitrary node. Motivated by applications in protocol processin...
Michael Benedikt, Alan Jeffrey
VCIP
2000
124views Communications» more  VCIP 2000»
13 years 9 months ago
Rendering of 3D-wavelet-compressed concentric mosaic scenery with progressive inverse wavelet synthesis (PIWS)
The concentric mosaics offer a quick solution to the construction and navigation of a virtual environment. To reduce the vast data amount of the concentric mosaics, a compression ...
Yunnan Wu, Lin Luo, Jin Li, Ya-Qin Zhang
ICCD
2003
IEEE
143views Hardware» more  ICCD 2003»
14 years 27 days ago
Aggressive Test Power Reduction Through Test Stimuli Transformation
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
Ozgur Sinanoglu, Alex Orailoglu
APCCM
2009
13 years 8 months ago
Synthesis of Orchestrators from Service Choreographies
Interaction topologies in service-oriented systems are usually classified into two styles: choreographies and orchestrations. In a choreography, services interact in a peer-to-pee...
Stephen McIlvenna, Marlon Dumas, Moe Thandar Wynn