115 search results - page 7 / 23 » AFTA: A Formal Delay Model for Functional Timing Analysis |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
SOFSEM
2007
Springer
14 years 1 months ago
2007
Springer
Digital technology is increasingly deployed in safety-critical situations. This calls for systematic design and verification methodologies that can cope with three major sources o...
CSCW
2006
ACM
14 years 1 months ago
2006
ACM
We evaluate response times, in N-user collaborations, of the popular centralized (client-server) and replicated (peer-to-peer) architectures, and a hybrid architecture in which ea...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...