72 search results - page 8 / 15 » Abridged addressing: a low power memory addressing strategy |
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
BMCBI
2007
13 years 7 months ago
2007
Background: New high throughput pyrosequencers such as the 454 Life Sciences GS 20 are capable of massively parallelizing DNA sequencing providing an unprecedented rate of output ...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
COMPCON
1994
IEEE
13 years 11 months ago
1994
IEEE
The Newton MessagePad Personal Digital Assistant (PDA) is the first in a class of devices distinguished by their pen-based user interface, communications capability, small size, a...
ATAL
2006
Springer
13 years 11 months ago
2006
Springer
We address the problem of learning in repeated N-player (as opposed to 2-player) general-sum games. We describe an extension to existing criteria focusing explicitly on such setti...