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» Abridged addressing: a low power memory addressing strategy
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LCTRTS
2010
Springer
14 years 2 months ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...
HIPC
1999
Springer
13 years 11 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
CDC
2010
IEEE
294views Control Systems» more  CDC 2010»
13 years 2 months ago
Adaptive self-triggered control over IEEE 802.15.4 networks
The communication protocol IEEE 802.15.4 is becoming pervasive for low power and low data rate wireless sensor networks (WSNs) applications, including control and automation. Never...
Ubaldo Tiberi, Carlo Fischione, Karl Henrik Johans...
EMSOFT
2007
Springer
14 years 1 months ago
Block recycling schemes and their cost-based optimization in nand flash memory based storage system
Flash memory has many merits such as light weight, shock resistance, and low power consumption, but also has limitations like the erase-before-write property. To overcome such lim...
Jongmin Lee, Sunghoon Kim, Hunki Kwon, Choulseung ...
GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
14 years 1 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...