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» Accelerating SIFT on parallel architectures
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DELTA
2010
IEEE
14 years 1 months ago
Algorithm Transformation for FPGA Implementation
— High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
Donald G. Bailey, Christopher T. Johnston
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
14 years 1 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
ISPAN
2005
IEEE
14 years 2 months ago
An FPGA-Based Floating-Point Jacobi Iterative Solver
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
Gerald R. Morris, Viktor K. Prasanna
PVG
2003
IEEE
138views Visualization» more  PVG 2003»
14 years 1 months ago
Sort-First, Distributed Memory Parallel Visualization and Rendering
While commodity computing and graphics hardware has increased in capacity and dropped in cost, it is still quite difficult to make effective use of such systems for general-purpos...
E. Wes Bethel, Greg Humphreys, Brian E. Paul, J. D...
PVLDB
2008
126views more  PVLDB 2008»
13 years 8 months ago
Parallelizing query optimization
Many commercial RDBMSs employ cost-based query optimization exploiting dynamic programming (DP) to efficiently generate the optimal query execution plan. However, optimization tim...
Wook-Shin Han, Wooseong Kwak, Jinsoo Lee, Guy M. L...