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HPCA
2008
IEEE
14 years 7 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
PPOPP
2006
ACM
14 years 29 days ago
Exploiting distributed version concurrency in a transactional memory cluster
We investigate a transactional memory runtime system providing scaling and strong consistency for generic C++ and SQL applications on commodity clusters. We introduce a novel page...
Kaloian Manassiev, Madalin Mihailescu, Cristiana A...
EUROPAR
2009
Springer
13 years 11 months ago
MyriXen: Message Passing in Xen Virtual Machines over Myrinet and Ethernet
Data access in HPC infrastructures is realized via user-level networking and OS-bypass techniques through which nodes can communicate with high bandwidth and low-latency. Virtualiz...
Anastassios Nanos, Nectarios Koziris
IHI
2012
217views Healthcare» more  IHI 2012»
12 years 2 months ago
Declarative privacy policy: finite models and attribute-based encryption
Regulations and policies regarding Electronic Health Information (EHI) are increasingly complex. Federal and State policy makers have called for both education to increase stakeho...
Peifung E. Lam, John C. Mitchell, Andre Scedrov, S...
DAC
2001
ACM
14 years 8 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...