An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced s...
Piet Engelke, Ilia Polian, Michel Renovell, Bernd ...
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
Successful failure analysis requires accurate fault diagnosis. This paper presents a method for diagnosing bridging faults that improves on previous methods. The new method uses s...
David B. Lavo, Brian Chess, Tracy Larrabee, F. Joe...
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, We...