48 search results - page 4 / 10 » Accurate timing analysis using SAT and pattern-dependent del... |
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper presents a two-step, RC-interconnect insensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to characterize a driver with the...
JPDC
2011
13 years 3 months ago
2011
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource ...
ISPD
2003
ACM
14 years 2 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...