This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi...
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performanc...
Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawren...
Abstract—Many applications in wireless sensor networks require communication performance that is both consistent and high quality. Unfortunately, performance of current network p...
Shan Lin, Gang Zhou, Kamin Whitehouse, Yafeng Wu, ...
We study the impact of user association policies on flow-level performance in interference limited wireless networks. Most research in this area has used static interference model...