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DATE
2004
IEEE
173views Hardware» more  DATE 2004»
14 years 11 days ago
An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation
We present our system-level co-simulation environment for mixed domain microsystems. The environment provides synchronization and cosimulation between the Chatoyant MOEMS (MicroEl...
D. K. Reed, Steven P. Levitan, J. Boles, Jose A. M...
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
14 years 3 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
ICS
2007
Tsinghua U.
14 years 2 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
HPCA
2004
IEEE
14 years 9 months ago
Signature Buffer: Bridging Performance Gap between Registers and Caches
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
Lu Peng, Jih-Kwon Peir, Konrad Lai
SBACPAD
2004
IEEE
105views Hardware» more  SBACPAD 2004»
13 years 10 months ago
Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance
High-performance processors employ aggressive speculation and prefetching techniques to increase performance. Speculative memory references caused by these techniques sometimes br...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...