11384 search results - page 57 / 2277 » Achieved IPC Performance |
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
In this paper we present a cost-effective, high bandwidth server I/O network architecture, named PaScal (Parallel and Scalable). We use the PaScal server I/O network to support da...
HPCA
2006
IEEE
14 years 2 months ago
2006
IEEE
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
PACS
2004
Springer
14 years 2 months ago
2004
Springer
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
ICPP
2003
IEEE
14 years 2 months ago
2003
IEEE
Aggressive hardware-based and software-based prefetch algorithms for hiding memory access latencies were proposed to bridge the gap of the expanding speed disparity between proces...