144 search results - page 5 / 29 » Adapting cache line size to application behavior |
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Dictionary code compression is a technique where long instructions in the memory are replaced with shorter code words used as index in a table to look up the original instructions...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
HPCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Main memory accesses continue to be a significant bottleneck for applications whose working sets do not fit in second-level caches. With the trend of greater associativity in seco...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
HIPC
1999
Springer
13 years 11 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...