67 search results - page 10 / 14 » Adaptive Aggregation on Chip Multiprocessors |
120
Voted
ISQED
2010
IEEE
15 years 2 months ago
2010
IEEE
Multiple use-case chip multiprocessor (CMP) applications require adaptive on-chip communication fabrics to cope with changing use-case performance needs. Networks-on-chip (NoC) ha...
123
Voted
MICRO
2007
IEEE
15 years 10 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
158
click to vote
HPCA
2011
IEEE
14 years 7 months ago
2011
IEEE
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...
111
Voted
MICRO
2006
IEEE
15 years 9 months ago
2006
IEEE
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
121
Voted
MICRO
2010
IEEE
15 years 1 months ago
2010
IEEE
Current trends signal an imminent crisis in the simulation of future CMPs (Chip MultiProcessors). Future micro-architectures will offer more and more thread contexts to execute pa...