67 search results - page 11 / 14 » Adaptive Aggregation on Chip Multiprocessors |
HPCA
2009
IEEE
14 years 10 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
HPCA
2008
IEEE
14 years 10 months ago
2008
IEEE
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
ISCA
2009
IEEE
14 years 4 months ago
2009
IEEE
Dynamic voltage and frequency scaling (DVFS) is a commonly-used powermanagement scheme that dynamically adjusts power and performance to the time-varying needs of running programs...
ISCA
2008
IEEE
14 years 4 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
DAGSTUHL
2006
13 years 11 months ago
2006
Current and future communications systems have to provide a large degree of flexibility e.g. to provide multi-service ability, seamless roaming, softinfrastructure upgrading, user-...