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» Adaptive Aggregation on Chip Multiprocessors
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VLDB
2007
ACM
79views Database» more  VLDB 2007»
14 years 10 months ago
Adaptive Aggregation on Chip Multiprocessors
John Cieslewicz, Kenneth A. Ross
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
14 years 4 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
ISCA
2006
IEEE
182views Hardware» more  ISCA 2006»
14 years 3 months ago
Cooperative Caching for Chip Multiprocessors
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Jichuan Chang, Gurindar S. Sohi
HPCA
2007
IEEE
14 years 4 months ago
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
Haakon Dybdahl, Per Stenström
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 3 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...