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» Adaptive Aggregation on Chip Multiprocessors
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ICCD
2011
IEEE
296views Hardware» more  ICCD 2011»
12 years 9 months ago
DPPC: Dynamic power partitioning and capping in chip multiprocessors
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
Kai Ma, Xiaorui Wang, Yefu Wang
CC
2010
Springer
190views System Software» more  CC 2010»
14 years 4 months ago
Is Reuse Distance Applicable to Data Locality Analysis on Chip Multiprocessors?
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
Yunlian Jiang, Eddy Z. Zhang, Kai Tian, Xipeng She...
MICRO
2008
IEEE
148views Hardware» more  MICRO 2008»
14 years 4 months ago
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
—Efficient sharing of system resources is critical to obtaining high utilization and enforcing system-level performance objectives on chip multiprocessors (CMPs). Although sever...
Ramazan Bitirgen, Engin Ipek, José F. Mart&...
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 6 months ago
Performance Efficiency of Context-Flow System-on-Chip Platform
Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective program...
Rami Beidas, Jianwen Zhu
INFORMATICALT
2006
154views more  INFORMATICALT 2006»
13 years 9 months ago
Efficient Adaptive Algorithms for Transposing Small and Large Matrices on Symmetric Multiprocessors
Matrix transpose in parallel systems typically involves costly all-to-all communications. In this paper, we provide a comparative characterization of various efficient algorithms f...
Rami Al Na'mneh, W. David Pan, Seong-Moo Yoo