61 search results - page 4 / 13 » Adaptive Cache Memories for SMT Processors |
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
ISCAPDCS
2004
13 years 10 months ago
2004
Hyperthreaded(HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by ex...
ISCA
1997
IEEE
14 years 1 months ago
1997
IEEE
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
IEEEINTERACT
2003
IEEE
14 years 2 months ago
2003
IEEE
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...