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EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
15 years 8 months ago
Quality considerations in delay fault testing
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
Alicja Pierzynska, Slawomir Pilarski
EURODAC
1995
IEEE
198views VHDL» more  EURODAC 1995»
15 years 8 months ago
On generating compact test sequences for synchronous sequential circuits
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Irith Pomeranz, Sudhakar M. Reddy
PTS
2004
88views Hardware» more  PTS 2004»
15 years 5 months ago
From Design to Test with UML: Applied to a Roaming Algorithm for Bluetooth Devices
The UML Testing Profile provides support for UML based model-driven testing. This paper introduces a methodology of how to use the testing profile in order to modify and extend an ...
Zhen Ru Dai, Jens Grabowski, Helmut Neukirchen, Ho...
WSC
2001
15 years 5 months ago
Usage testing of military simulation systems
Scalability and input domain explosion make it impossible to exhaustively test simulation systems. Improved methods such as statistical usage testing are needed to provide quantit...
Gwendolyn H. Walton, Robert M. Patton, Douglas J. ...
CASCON
1996
77views Education» more  CASCON 1996»
15 years 5 months ago
Class testing and code-based criteria
This paper de nes three levels of requirements for adequate code-based class testing, examining the eectiveness of traditional testing criteria in the context of object-oriented (...
Pei Hsia, Xiaolin Li, David Chenho Kung