We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signicantly aect the actual...
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
The UML Testing Profile provides support for UML based model-driven testing. This paper introduces a methodology of how to use the testing profile in order to modify and extend an ...
Zhen Ru Dai, Jens Grabowski, Helmut Neukirchen, Ho...
Scalability and input domain explosion make it impossible to exhaustively test simulation systems. Improved methods such as statistical usage testing are needed to provide quantit...
Gwendolyn H. Walton, Robert M. Patton, Douglas J. ...
This paper denes three levels of requirements for adequate code-based class testing, examining the eectiveness of traditional testing criteria in the context of object-oriented (...