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36

EURODAC
1995
IEEE

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On generating compact test sequences for synchronous sequential circuits

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On generating compact test sequences for synchronous sequential circuits

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We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test application time and memory requirements. The proposed procedure constructs a test sequence using a combination of fault-independent and faultoriented criteria. Experimental results are presented to demonstrate its effectiveness.

Irith Pomeranz, Sudhakar M. Reddy

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EURODAC 1995 | Short Test Sequences | Synchronous Sequential Circuits | Test Application Time | VHDL |

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Added	26 Aug 2010
Updated	26 Aug 2010
Type	Conference
Year	1995
Where	EURODAC
Authors	Irith Pomeranz, Sudhakar M. Reddy

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