On generating compact test sequences for synchronous sequential circuits

We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test application time and memory requirements. The proposed procedure constructs a test sequence using a combination of fault-independent and faultoriented criteria. Experimental results are presented to demonstrate its effectiveness.

• Type: Conference
• Year: 1995
• Where: EURODAC
• Authors: Irith Pomeranz, Sudhakar M. Reddy
• Keywords: EURODAC 1995, Short Test Sequences, Synchronous Sequential Circuits, Test Application Time, VHDL