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130
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DATE
2006
IEEE
78views Hardware» more  DATE 2006»
15 years 9 months ago
Functional constraints vs. test compression in scan-based delay testing
We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many po...
Ilia Polian, Hideo Fujiwara
144
Voted
DSD
2005
IEEE
106views Hardware» more  DSD 2005»
15 years 9 months ago
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
133
Voted
XPU
2004
Springer
15 years 9 months ago
Generative Acceptance Testing for Difficult-to-Test Software
Abstract. While there are many excellent acceptance testing tools and frameworks available today, this paper presents an alternative approach, involving generating code from tests ...
Jennitta Andrea
115
Voted
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
15 years 9 months ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja...
127
Voted
ITC
2002
IEEE
135views Hardware» more  ITC 2002»
15 years 8 months ago
Test Coverage: What Does It Mean When a Board Test Passes?
ct Characterizing board test coverage as a percentage of devices or nodes having tests does not accurately portray coverage, especially in a limited access testing environment that...
Kathy Hird, Kenneth P. Parker, Bill Follis