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ISCA
2005
IEEE
117views Hardware» more  ISCA 2005»
15 years 11 months ago
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
Amir Roth
132
Voted
FPGA
2005
ACM
95views FPGA» more  FPGA 2005»
15 years 11 months ago
The Stratix II logic and routing architecture
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaugh...
ISMIR
2005
Springer
196views Music» more  ISMIR 2005»
15 years 11 months ago
ACE: A Framework for Optimizing Music Classification
This paper presents ACE (Autonomous Classification Engine), a framework for using and optimizing classifiers. Given a set of feature vectors, ACE experiments with a variety of cla...
Cory McKay, Rebecca Fiebrink, Daniel McEnnis, Bein...
ASIACRYPT
2004
Springer
15 years 11 months ago
Eliminating Random Permutation Oracles in the Even-Mansour Cipher
Abstract. Even and Mansour [EM97] proposed a block cipher construction that takes a publicly computable random permutation oracle P and XORs different keys prior to and after appl...
Craig Gentry, Zulfikar Ramzan
EMSOFT
2004
Springer
15 years 11 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande