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TVLSI
2010
13 years 2 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
EVOW
2008
Springer
13 years 9 months ago
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks
The design of computer architectures requires the setting of multiple parameters on which the final performance depends. The number of possible combinations make an extremely huge ...
Pedro A. Castillo, Antonio Miguel Mora, Juan Juli&...
LCN
2008
IEEE
14 years 1 months ago
Real-time performance analysis of Adaptive Link Rate
—High speed links are widely deployed in modern day computer networks to meet the ever growing needs for increasing data bandwidth. However, with the increase in the link rate, t...
Baoke Zhang, Karthik Sabhanatarajan, Ann Gordon-Ro...
PERCOM
2010
ACM
13 years 11 months ago
Negotiate power and performance in the reality of RFID systems
—Recent years have witnessed the wide adoption of the RFID technology in many important application domains including logistics, inventory, retailing, public transportation, and ...
Xunteng Xu, Lin Gu, Jianping Wang, Guoliang Xing
PCRCW
1997
Springer
13 years 11 months ago
Power/Performance Trade-offs for Direct Networks
High performance portable and space-borne systems continue to demand increasing computation speeds while concurrently attempting to satisfy size, weight, and power constraints. As...
Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchil...