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» Adaptive insertion policies for high performance caching
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MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
14 years 2 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
MICRO
2006
IEEE
162views Hardware» more  MICRO 2006»
14 years 1 months ago
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...
Ranjith Subramanian, Yannis Smaragdakis, Gabriel H...
ICPP
2008
IEEE
14 years 1 months ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
EUROPAR
2008
Springer
13 years 9 months ago
Low-Cost Adaptive Data Prefetching
We explore different prefetch distance-degree combinations and very simple, low-cost adaptive policies on a superscalar core with a high bandwidth, high capacity on-chip memory hie...
Luis M. Ramos, José Luis Briz, Pablo E. Ib&...
IPCCC
1999
IEEE
13 years 11 months ago
Management policies for non-volatile write caches
Many computer hardware and software architectures buffer data in memory to improve system performance. Volatile disk or file caches are sometimes used to delay the propagation of ...
Theodore R. Haining, Darrell D. E. Long