114 search results - page 9 / 23 » Address Register Assignment for Reducing Code Size |
ASPLOS
2008
ACM
13 years 8 months ago
2008
ACM
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
ASPLOS
1998
ACM
13 years 11 months ago
1998
ACM
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
ISCA
2003
IEEE
14 years 4 hour ago
2003
IEEE
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
IPPS
2006
IEEE
14 years 22 days ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
HPCA
2001
IEEE
14 years 7 months ago
2001
IEEE
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...