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» Address generation for memories containing multiple arrays
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ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
14 years 27 days ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...
GECCO
2007
Springer
345views Optimization» more  GECCO 2007»
14 years 1 months ago
A novel approach to automatic music transcription using electronic synthesis and genetic algorithms
This paper presents a novel approach to the problem of automatic music transcription using electronic synthesis with genetic algorithms. Although the problem is well known and di...
Gustavo Reis, Francisco Fernández de Vega
IPPS
2010
IEEE
13 years 5 months ago
Restructuring parallel loops to curb false sharing on multicore architectures
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Santosh Sarangkar, Apan Qasem
IPPS
2005
IEEE
14 years 1 months ago
Automatic Support for Irregular Computations in a High-Level Language
The problem of writing high performance parallel applications becomes even more challenging when irregular, sparse or adaptive methods are employed. In this paper we introduce com...
Jimmy Su, Katherine A. Yelick
AXMEDIS
2006
IEEE
215views Multimedia» more  AXMEDIS 2006»
14 years 1 months ago
Distributed Architectures for High Performance and Privacy-Aware Content Generation and Delivery
The increasing heterogeneity of mobile client devices used to access the Web requires run-time adaptations of the Web contents. A significant trend in these content adaptation se...
Claudia Canali, Michele Colajanni, Riccardo Lancel...