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ITC
2003
IEEE
222views Hardware» more  ITC 2003»
14 years 1 months ago
Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
Mahesh A. Iyer
STOC
1989
ACM
96views Algorithms» more  STOC 1989»
14 years 14 days ago
Optimal Size Integer Division Circuits
Division is a fundamental problem for arithmetic and algebraic computation. This paper describes Boolean circuits of bounded fan-in for integer division  nding reciprocals that...
John H. Reif, Stephen R. Tate
GLVLSI
2009
IEEE
142views VLSI» more  GLVLSI 2009»
14 years 3 months ago
Hardware-accelerated gradient noise for graphics
A synthetic noise function is a key component of most computer graphics rendering systems. This pseudo-random noise function is used to create a wide variety of natural looking te...
Josef B. Spjut, Andrew E. Kensler, Erik Brunvand
MP
2008
135views more  MP 2008»
13 years 8 months ago
A path to the Arrow-Debreu competitive market equilibrium
: We present polynomial-time interior-point algorithms for solving the Fisher and Arrow-Debreu competitive market equilibrium problems with linear utilities and n players. Both of ...
Yinyu Ye
DAC
1996
ACM
14 years 17 days ago
Bit-Level Analysis of an SRT Divider Circuit
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
Randal E. Bryant