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CIIA
2009
13 years 11 months ago
Physical Synthesis for CPLD Architectures
In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architectu...
Sid-Ahmed Senouci
CAD
2006
Springer
13 years 10 months ago
Robust parameter synthesis for planar higher pair mechanical systems
We present a parameter synthesis algorithm for planar, higher pair mechanical systems. The input is a parametric model of a mechanical system (part shapes and configurations) with...
Min-Ho Kyung, Elisha Sacks
ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
14 years 4 months ago
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Ch...
DAC
1997
ACM
14 years 2 months ago
COSYN: Hardware-Software Co-Synthesis of Embedded Systems
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...
Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. J...
DAC
2005
ACM
14 years 11 months ago
Temperature-aware resource allocation and binding in high-level synthesis
Physical phenomena such as temperature have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with futu...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...