Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis

Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, power-ground noise etc., consume increasing proportion of the clock cycle. Thus, reducing the clock skew variations is one of the most important objectives of any high-speed clock distribution methodology. Inserting cross-links in a given clock tree is one way to reduce unwanted clock skew variations [1–6]. However, most of the existing methods like [1–5] use empirical methods and do not use delay/skew variation information to select the links to be inserted. This can result in ineffective links being inserted. The work of [6] considers the delay variation directly, but it is very slow even for small clock trees. In this paper, we propose a fast link insertion algorithm that considers the delay variation information directly during link selection process. Our algorithm inserts links only in the parts of the...

• Type: Conference
• Year: 2007
• Where: ISQED
• Authors: Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan
• Keywords: Clock, Clock Skew, Clock Skew Variations, Hardware, ISQED 2007