We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
–An FPGA switch box is said to be hyper-universal if it is routable for all possible surrounding multi-pin net topologies satisfying the routing resource constraints. It is desir...
—In this paper, we address the scheduling problem for Clos-network switches with no buffers at the central stage. Existing scheduling (dispatching) algorithms for this type of sw...
Mei Yang, Mayauna McCullough, Yingtao Jiang, Jun Z...
Abstract. The hotspot seriously degrades the performance of a parallel algorithm but there have not been many methods proposed for this problem. Without modification of mesh topolo...
Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of th...