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FPGA
2005
ACM
158views FPGA» more  FPGA 2005»
14 years 2 months ago
Automated synthesis for asynchronous FPGAs
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...
Song Peng, David Fang, John Teifel, Rajit Manohar
BMCBI
2010
143views more  BMCBI 2010»
13 years 9 months ago
An efficient biological pathway layout algorithm combining grid-layout and spring embedder for complicated cellular location inf
Background: Graph drawing is one of the important techniques for understanding biological regulations in a cell or among cells at the pathway level. Among many available layout al...
Kaname Kojima, Masao Nagasaki, Satoru Miyano
ASPLOS
2006
ACM
14 years 2 months ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
ISAAC
2001
Springer
123views Algorithms» more  ISAAC 2001»
14 years 1 months ago
Labeling Subway Lines
Abstract. Graphical features on map, charts, diagrams and graph drawings usually must be annotated with text labels in order to convey their meaning. In this paper we focus on a pr...
Maria Angeles Garrido, Claudia Iturriaga, Alberto ...
COMPGEOM
2006
ACM
14 years 2 months ago
An optimal-time algorithm for shortest paths on a convex polytope in three dimensions
We present an optimal-time algorithm for computing (an implicit representation of) the shortest-path map from a fixed source s on the surface of a convex polytope P in three dime...
Yevgeny Schreiber, Micha Sharir