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ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
14 years 4 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid
ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
14 years 1 months ago
Glitch-aware output switching activity from word-level statistics
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...
VL
2008
IEEE
105views Visual Languages» more  VL 2008»
14 years 1 months ago
What's in a mashup? And why? Studying the perceptions of web-active end users
Mashups – web applications that integrate multiple data sources or APIs into one interface – have attracted considerable attention in recent years. The availability of web-bas...
Nan Zang, Mary Beth Rosson
CC
2005
Springer
120views System Software» more  CC 2005»
14 years 1 months ago
Data Slicing: Separating the Heap into Independent Regions
In this paper, we present a formal description of data slicing, which is a type-directed program transformation technique that separates a program’s heap into several independent...
Jeremy Condit, George C. Necula
FCCM
2000
IEEE
144views VLSI» more  FCCM 2000»
13 years 12 months ago
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines
Mapping computations written in high-level programming languages to FPGA-based computing engines requires programmers to generate the datapath responsible for the core of the comp...
Pedro C. Diniz, Joonseok Park